Mask and method for making the same, and method for making semiconductor device

ABSTRACT

A mask capable of alignment by the TTR system and complementary division and having a high strength, a method of production of the same, and a method of production of a semiconductor device having a high pattern accuracy are provided. A stencil mask having stripe-shaped grid lines  4  formed by etching a silicon wafer in four sub-regions A to D on a membrane, having the stripes arranged point symmetrically about a center of the membrane, and having all of the grid lines connected to other grid lines or the silicon wafer around the membrane (support frame), a method of production of the same, and a method of production of a semiconductor device using the mask.

TECHNICAL FIELD

[0001] The present invention relates to a mask used for production of asemiconductor device and a method of production of the same and a methodof production of a semiconductor device.

BACKGROUND ART

[0002] Low energy electron beam proximity projection lithography (LEEPL)is one of the next generation exposure techniques taking the place ofphotolithography. LEEPL uses a stencil mask having a membrane of severalhundreds of nm thickness formed with holes corresponding to devicepatterns. A “stencil mask” means a mask formed with holes passingthrough its membrane. No material exists in the spaces in the holes ofthe stencil mask.

[0003] In LEEPL, the mask is arranged just above a wafer so as to make adistance between the mask and wafer several tens of μm or so. Patternparts of the mask are scanned by an electron beam of several tens of keVto transfer the patterns on the wafer (T. Utsumi, Journal of VacuumScience and Technology, B17, 2897 (1999)).

[0004] However, the mask for LEEPL has a problem of distortion of thepatterns due to internal stress when the membrane is made larger in sizeand the membrane flexes by its weight. One method to solve the problemis to use diamond or another material having a high Young's modulus asthe membrane material (see Japanese Unexamined Patent Publication(Kokai) No. 2001-77016). For decreasing the flex of the membrane due toits weight, the internal stress of the membrane has to be increasedalong with increase of the membrane size. Therefore, enlargement of themembrane is limited by itself.

[0005] Another method is the method of supporting a sub-sectionedmembrane by a grid line (strut) structure. This is employed in masksused for SCALPEL (scattering with angular limitation in projectionelectron-beam lithography), PREVAIL (projection exposure with variableaxis immersion lenses), and an EB stepper (for example, L. R. Harriott,Journal of Vacuum Science and Technology, B 15, 2130 (1997); H. C.Pfeiffer, Japanese Journal of Applied Physics, 34, 6658 (1995)).

[0006]FIG. 1 is a schematic view of an EB stepper mask currentlyproposed. As shown in FIG. 1, grid lines 11 divide and support amembrane 12. The membrane 12 is provided with holes (not shown) indevice patterns.

[0007] The mask shown in FIG. 1 is made from for example an SOI (siliconon insulator or semiconductor on insulator) wafer comprised of a siliconwafer formed with a silicon active layer via a silicon oxide film. Thesilicon active layer on the surface of the SOI wafer is used as themembrane 12, while the grid lines 11 are formed by etching the siliconwafer from the rear surface of the silicon active layer.

[0008] According to the mask structure shown in FIG. 1, the membrane 12is divided into small sections which are supported by the stiff gridlines 11. Therefore, the problem of the increase in deflection of themembrane along with the increase in the membrane size as observed in themask described in Japanese Unexamined Patent Publication (Kokai) No.2001-77016 etc. does not occur.

[0009] However, the mask structure with the grid lines 11 formedregularly in a square mesh as shown in FIG. 1 cannot be applied as it isto LEEPL. In LEEPL, first, a mask region corresponding to one or morechips is scanned by an electron beam.

[0010] After the exposure is finished, a wafer stage is moved by exactlya distance corresponding to the chip size or a whole multiple of thesame and exposure performed again. This is repeated to expose chipsarranged over the entire surface of the wafer (step and repeatexposure). As shown in FIG. 1, when the grid lines 11 are arranged in asquare mesh, regions right below the grid lines cannot be exposed.

[0011] Therefore, rather than dividing the entire mask region uniformlyin a mesh, the method of dividing the membrane of the mask 21 into foursub-regions A to D as shown in FIG. 2 and forming the grid lines (seeFIG. 1) by these regions so that the meshes are offset may beconsidered. Here, each of the sub-regions A to D is a mask regioncorresponding to one or more chips (chip transfer region). The waferstage is moved in units of these sub-regions.

[0012]FIG. 3 shows an example of arrangement of the grid lines 11 on thesub-regions A to D of the membrane of FIG. 2. In FIG. 3, the regionsdivided by the orthogonal x-axis and y-axis correspond to thesub-regions A to D of FIG. 2. As shown in FIG. 3, for convenience, thesub-regions are assumed to be squares of 10×10 blocks obtained bydividing them in a mesh.

[0013] In the example shown in FIG. 3, the 5×5 block parts surrounded bydotted lines in the sub-regions A to D correspond to single chips. Whenmoving the wafer stage to the sub-regions A to D, the parts surroundedby the dotted lines are multiply exposed. The arrangement of the gridlines 11 in these sub-regions is a repetition of the arrangement of thegrid lines 11 in the portions surrounded by the dotted lines (transferregions).

[0014] As described above, since the regions right below the grid linescannot be exposed, if linking the 5×5 blocks surrounded by the dottedlines with a 5 row×5 column table and summarizing which sub-region isexposed at each block (namely, in which sub-region a pattern can beformed), the result is shown in Table 1. TABLE 1 A D A B A B D B D A B DA C A B C A B C B C A B A C D A B C A B C D B C D A B D C D B C B C D BC D B D A C D A B C A C D C D A D

[0015] In the case of a stencil mask, if forming a for exampledonut-like pattern, the center part surrounded by the pattern cannot besupported. Alternatively, when forming a long pattern etc. in onedirection etc., the membrane will warp and the positional accuracy ofthe pattern will become lower. Therefore, the pattern is divided and aplurality of complementary masks are formed. The complementary masks areused for multiple exposure to transfer the pattern complementarily(complementary division).

[0016] Here, the “complementary masks” mean a plurality of masks formedwith different patterns (complementarily divided patterns) comprised ofparts of patterns obtained by dividing the pattern of a certain region.By exposing specific regions of the complementary masks superposed atthe same place of the exposed object (usually a wafer), the patternbefore division is restored and transferred to the exposed object.

[0017] For example, when arranging the grid lines shown in FIG. 3, asshown in Table 1, it is possible to form patterns in at least twosub-regions for each block. Therefore, it is possible to link two ormore sub-regions with any position of a chip. By multiple exposuresuperposing four sub-regions on the same mask, it is possible totransfer any device pattern including a donut-like pattern to the wafer.

[0018] However, when combining the masks arranged with the grid lines asshown in FIG. 3 with certain types of alignment methods, problems mayarise. With LEEPL, the mask and wafer are in proximity at a distance ofseveral tens of μm, so an alignment optical system cannot be placedbetween the mask and the wafer.

[0019] Consequently, the through-the-reticle (TTR) alignment system asshown in FIG. 4 (Japanese Patent No. 3101582) is used. As shown in FIG.4, the surface of the wafer 31 is formed with wafer-side alignment marks32. On the other hand, the mask 33 is also formed with mask-sidealignment marks 34. The mask-side alignment marks 34 can be eitherapertures passing through the membrane or recesses formed only in thesurface of the membrane.

[0020] Alignment light strikes the wafer-side alignment marks 32 and themask-side alignment marks 34. Light L_(W) reflected from the wafer-sidealignment marks 32 and Light L_(M) reflected from the mask-sidealignment marks 34 are detected. The relative position of the lightL_(W) and the light L_(M) is used for alignment of the mask 33 and thewafer 31.

[0021] By arranging four alignment detection system (X₁, X₂, Y₁, Y₂) atthe four corners of the mask as shown in FIG. 5 and performing alignmentas shown in FIG. 4, distortion of the mask regions corresponding to thechips can be completely determined. According to the TTR alignmentsystem, the alignment optical system is not placed between the mask andthe wafer, so it becomes possible to constantly detect the alignmentmarks even during electron beam exposure and compensate for chipdistortion in real time.

[0022] When forming grid lines on a mask in a square mesh as shown inFIG. 1 or FIG. 3, if performing alignment by the TTR alignment system,alignment becomes impossible under specific conditions. FIG. 6 is across-sectional view showing one of pattern formation regions surroundedby the grid lines 11.

[0023] As shown in FIG. 6, when a detection angle θ of alignment light Lmeasured from a mask normal line direction z exceeds a specific criticalangle θa determined by the interval and height of the grid lines 11 andpositions of the alignment marks 34, the grid lines 11 and the alignmentlight L (light reflected from the mask-side alignment marks 34)interfere so the alignment light L can no longer be detected.

DISCLOSURE OF THE INVENTION

[0024] The present invention was made in consideration of the aboveproblems and has as its object the provision of a mask able to performalignment by the TTR system and transfer complementarily dividedpatterns and having a sufficient membrane strength and a method ofproduction of the same.

[0025] Further, the present invention has as its object the provision ofa method of production of a semiconductor device improving the alignmentaccuracy in a lithography step and able to transfer a fine pattern witha high accuracy.

[0026] To achieve the above objects, the mask of the present inventionis characterized by comprising a support frame; a thin film made formedthinner than said support frame and surrounded by said support frame; afirst sub-region of a plurality of sub-regions obtained by dividing saidthin film by a plurality of lines including a first line passing througha reference point consisting of one point on said thin film andextending in a first direction and a second line orthogonal to the firstline at the reference point and extending in a second direction; asecond sub-region adjacent to said first sub-region in the firstdirection; a third sub-region adjacent to said first sub-region in thesecond direction; a fourth sub-region adjacent to said second sub-regionin the second direction and adjacent to said third sub-region in thefirst direction; a first group of grid lines comprised of at least onegrid line extending on said first sub-region in a second direction andhaving one end connected to one of a third group of grid lines toreinforce said thin film, said first group of grid lines including agrid line contacting the second line; a second group of grid linescomprised of at least one grid line extending on said second sub-regionin the first direction and having one end connected to one of said firstgroup of grid lines to reinforce said thin film, said second group ofgrid lines including a grid line contacting the first line; said thirdgroup of grid lines comprised of at least one grid line extending onsaid third sub-region in the first direction and having one endconnected to one of a fourth group of grid lines to reinforce said thinfilm, said third group of grid lines including a grid line contactingthe first line; said fourth group of grid lines comprised of at leastone grid line extending on said fourth sub-region in the seconddirection and having one end connected to one of said second group ofgrid lines to reinforce said thin film, said fourth group of grid linesincluding a grid line contacting the second line; a first apertureformed at a part of a portion other than the grid lines in the firstsub-region; and a second aperture formed at a part of a portion otherthan the grid lines in at least one sub-region of the second to fourthsub-regions.

[0027] Preferably, the first aperture and the second aperture formpatterns complementarily. Preferably, the grid lines are formed at equalintervals in each of the sub-regions and the first to fourth sub-regionsare squares or rectangles the same as each other in shape and size.Further, preferably the grid lines of at least one of group among thefirst to fourth groups are formed to having other ends connected to thesupport frame. Preferably, the first and second apertures are holesthrough which a charged particle beam passes. Preferably, the first tofourth sub-regions are divided into a plurality of chip transfer regionsthe same in shape and size by at least one first division line parallelto the first line and at least one second division line parallel to thesecond line. Preferably, the mask has an alignment mark formed at a partof a portion other than the grid lines in the first to fourthsub-regions. Preferably, the alignment mark is formed at a furthest partfrom the reference point.

[0028] Due to this, the problem of the grid lines blocking the alignmentlight so alignment becoming impossible when aligning the photosensitivesurface and the mask by the TTR system is solved. Therefore, it becomespossible to transfer fine patterns with a high accuracy by for exampleLEEPL.

[0029] Further, to achieve the above objects, the method of productionof a mask of the present invention is characterized by comprising thesteps of forming a support frame around a thin film, forming grid linesreinforcing said thin film at a part on one surface of said thin film,and forming apertures in the thin film at portions other than the gridlines, wherein said step of forming the grid lines comprising the stepof forming a first group of grid lines in a first sub-region of saidthin film, forming a second group of grid lines in a second sub-regionof said thin film, forming a third group of grid lines in a thirdsub-region of said thin film, and forming a fourth group of grid linesin a fourth sub-region of said thin film; said first sub-region is oneof a plurality of sub-regions obtained by dividing said thin film by aplurality of lines including a first line passing through a referencepoint consisting of one point on said thin film and extending in a firstdirection and a second line orthogonal to the first line at thereference point and extending in a second direction; said secondsub-region is a sub-region adjacent to said first sub-region in thefirst direction, said third sub-region is a sub-region adjacent to saidfirst sub-region in the second direction, said fourth sub-region is asub-region adjacent to said second sub-region in the second directionand adjacent to said third sub-region in the first direction, said firstgroup of grid lines is comprised of at least one grid line extending onthe first sub-region in the second direction and having one endconnected to one of a third group of grid lines to reinforce the thinfilm and including a grid line contacting the second line, said secondgroup of grid lines is comprised of at least one grid line extending onthe second sub-region in the first direction and having one endconnected to one of the first group of grid lines to reinforce the thinfilm and includes a grid line contacting the first line, said thirdgroup of grid lines is comprised of at least one grid line extending onthe third sub-region in the first direction and having one end connectedto one of a fourth group of grid lines to reinforce the thin film andincludes a grid line contacting the first line, said fourth group ofgrid lines is comprised of at least one grid line extending on thefourth sub-region in the second direction and having one end connectedto one of the second group of grid lines to reinforce the thin film andincludes a grid line contacting the second line, and the step of formingthe apertures comprises forming a first aperture at a part of a portionother than the grid lines in the first sub-region and forming a secondaperture at a part of a portion other than the grid lines in at leastone sub-region of the second to fourth sub-regions.

[0030] Due to this, it becomes possible to produce a mask in which analignment light is not blocked by grid lines when aligning thephotosensitive surface and the mask by the TTR system. According to themethod of production of a mask of the present invention, it becomespossible to produce a mask able to transfer fine patterns with a highaccuracy.

[0031] Further, to achieve the above objects, the method of productionof a semiconductor device of the present invention comprises an exposurestep of irradiating a charged particle beam, radiation, or a light rayon a photosensitive surface via a mask, comprising a first exposure stepof irradiating a charged particle beam, radiation, or a light ray on aphotosensitive surface via a mask comprising a support frame, a thinfilm made formed thinner than said support frame and surrounded by saidsupport frame, a first sub-region of a plurality of sub-regions obtainedby dividing said thin film by a plurality of lines including a firstline passing through a reference point consisting of one point on saidthin film and extending in a first direction and a second lineorthogonal to the first line at the reference point and extending in asecond direction, a second sub-region adjacent to said first sub-regionin the first direction, a third sub-region adjacent to said firstsub-region in the second direction, a fourth sub-region adjacent to saidsecond sub-region in the second direction and adjacent to said thirdsub-region in the first direction, a first group of grid lines comprisedof at least one grid line extending on said first sub-region in a seconddirection and having one end connected to one of a third group of gridlines to reinforce said thin film, said first group of grid linesincluding a grid line contacting the second line, a second group of gridlines comprised of at least one grid line extending on said secondsub-region in a first direction and having one end connected to one ofsaid first group of grid lines to reinforce said thin film, said secondgroup of grid lines including a grid line contacting the first line,said third group of grid lines comprised of at least one grid lineextending on said third sub-region in the first direction and having oneend connected to one of a fourth group of grid lines to reinforce saidthin film, said third group of grid lines including a grid linecontacting the first line, said fourth group of grid lines comprised ofat least one grid line extending on said fourth sub-region in a seconddirection and having one end connected to one of said second group ofgrid lines to reinforce said thin film, said fourth group of grid linesincluding a grid line contacting the second line, a first apertureformed at a part of a portion other than the grid lines in the firstsub-region, and a second aperture formed at a part of a portion otherthan the grid lines in at least one sub-region of the second to fourthsub-regions, said first exposure step conducting the first exposuresuperposing the first sub-region at a predetermined position of thephotosensitive surface to transfer the first aperture in thepredetermined position, and a second exposure step of performing secondexposure superposing one of the sub-regions including the secondaperture to a predetermined position to transfer the second aperture inthe predetermined position.

[0032] Preferably, said mask comprises a mask-side alignment mark at apart of a portion other than the grid lines in the first to fourthsub-regions and said method further comprises, before said firstexposure step, forming in advance a wafer-side alignment mark detectablevia the mask on said photosensitive surface or beneath saidphotosensitive surface and comprises, before each exposure step, atleast one of the steps of irradiating light in the first direction to asub-region including said grid lines extending in the first direction soas to detect positions of light reflected from the mask-side alignmentmark and light reflected from the photosensitive surface-side alignmentmark to align the mask and the photosensitive surface and irradiatinglight in the second direction to a sub-region including said grid linesextending in the second direction so as to detect positions of lightreflected from the mask-side alignment mark and light reflected from thephotosensitive surface-side alignment mark to align the mask and thephotosensitive surface. Preferably, the alignment is conductedconcurrently with the exposure.

[0033] Due to this, it becomes possible to align the photosensitivesurface and the mask by the TTR system in the lithography step.According to the present invention, the alignment light is not blockedby grid lines of the mask, so alignment can be performed with a highaccuracy.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1 is a perspective view of a conventional mask.

[0035]FIG. 2 is an example of dividing a membrane of a mask into aplurality of sub-regions.

[0036]FIG. 3 is an example showing a grid lines arrangement of a mask.

[0037]FIG. 4 is a schematic view of a TTR alignment system.

[0038]FIG. 5 is a plane view of an example of arrangement of analignment optical system.

[0039]FIG. 6 is a schematic view of alignment using a conventional mask.

[0040]FIG. 7 is a top view of a mask of the present invention.

[0041]FIG. 8 is a cross-sectional view along a-a′ of FIG. 7.

[0042]FIG. 9A is an enlarged view of the portion of the membrane 3 ofFIG. 7, while FIG. 9B and FIG. 9C are views of examples of mask-sidealignment marks.

[0043]FIG. 10 shows the results of calculation of the relationshipbetween a membrane size and a maximum bending moment of the membrane.

[0044]FIG. 11 is a schematic view of alignment using the mask of thepresent invention.

[0045]FIG. 12 is a flow chart of a method of production of asemiconductor device of the present invention.

[0046]FIG. 13 is a top view of the mask of the present invention.

[0047]FIG. 14 is a top view of an example of arrangement of sub-regionsin the mask of the present invention.

[0048]FIG. 15 is a top view of an example of arrangement of sub-regionsin the mask of the present invention.

[0049]FIG. 16 is a top view of an example of arrangement of sub-regionsin the mask of the present invention.

[0050]FIG. 17 is a schematic view of an electron beam exposure system towhich the mask of the present invention is applied.

[0051]FIG. 18 is a schematic view of another electron beam exposuresystem to which the mask of the present invention is applied.

BEST MODE FOR CARRYING OUT THE INVENTION

[0052] Below, embodiments of a mask and a method of production thereofand a method of production of a semiconductor device of the presentinvention will be described with reference to the accompanying drawings.

[0053]FIG. 7 is a top view of a mask of the present embodiment. The maskof the present embodiment is preferably used for LEEPL. As shown in FIG.7, a stencil mask 1 is formed by using for example a silicon wafer 2formed in its center part with a membrane 3. The stencil mask is a maskformed with holes passing through its membrane. No material exists in aspace in the holes of the stencil mask.

[0054] The silicon wafer 2 at the circumference of the membrane 3 isused as a support frame reinforcing the strength of the membrane 3. Themembrane 3 includes grid lines (struts) 4 integrated with thesurrounding silicon wafer 2 and pattern formation regions 5 surroundedby the grid lines 4. The grid lines 4 are comprised of protruding partsformed in bar shapes or line shapes on the membrane 3. The membrane 3substantially becomes thicker at parts formed with the grid lines 4. Dueto this, the membrane 3 is reinforced and deflection of the membrane 3due to its weight is prevented. The material of the grid lines 4 doesnot necessarily have to be same as the material of the support frame,but the support frame and the grid lines 4 can be formed easily in thesame step by dry etching the silicon wafer 2. In this case, thematerials become the same.

[0055]FIG. 8 is a cross-sectional view along a-a′ of FIG. 7. As shown inFIG. 8, a pattern formation region of the membrane 3 surrounded by thegrid lines 4 is formed with holes 6 corresponding to the devicepatterns. Also, parts of the pattern formation region are formed withmask-side alignment marks.

[0056] The stencil mask of the present embodiment shown in FIG. 7 andFIG. 8 is formed by using a for example SOI wafer comprised of a siliconwafer 2 formed with a silicon layer (membrane 3) via a silicon oxidefilm 7. The silicon wafer 2 is etched from a rear surface of themembrane 3 to form the grid lines 4. The silicon oxide film 7 is used asan etching stopper layer in etching of the silicon wafer 2. The holes 6are formed by etching the membrane 3. Also, the stencil mask can beformed by a method other than the above method.

[0057] The stencil mask of the present embodiment satisfies thefollowing three conditions. The first condition is that the membrane besupported by the grid lines. The second condition is thatcomplementarily divided patterns can be exposed efficiently bystep-and-repeat exposure of whole multiples of the chip size. The thirdcondition is that the optical path of the alignment optical system fordetecting the alignment marks on the wafer via the membrane notinterfere with the grid lines.

[0058] In the case of the above mask structure shown in FIG. 1, thefirst condition is satisfied. However, when dividing the membrane of thestructure shown in FIG. 1 into four sub-regions as shown in FIG. 2,positions formed with grid lines are superposed at the four sub-regions.Therefore, the complementarily divided patterns cannot be formed in thefour sub-regions A to D, so the second condition is not satisfied. Also,as shown in FIG. 6, the third condition is not satisfied.

[0059] When using the mask structure shown in FIG. 3, the first and thesecond conditions are satisfied. However, as shown in FIG. 6, the thirdcondition is not satisfied.

[0060]FIG. 9A shows enlarged the arrangement of grid lines at a stencilmask of the present embodiment. The hatched parts of FIG. 9A show thepattern formation regions 5 of FIG. 7, while portions sandwiched betweenthe pattern formation regions 5 show the grid lines 4. An exposureregion is divided into four sub-regions A to D by an x-axis and ay-axis. In the sub-regions A and D located on a diagonal, the grid lines4 are arranged symmetrically with respect to the origin O. The gridlines 4 in the sub-regions A and D extend in the x-direction (firstdirection). In the same manner, in the sub-regions B and C, the gridlines 4 are arranged symmetrically with respect to the origin O. Thegrid lines 4 in the sub-regions B and C extend in the y-direction(second direction).

[0061] The mask is divided into four sub-regions for the followingreasons. A mask having no grid lines is large in deflection of themembrane due to its weight so as to displace the pattern and difficultto be used as a mask. Consequently, it becomes necessary to form gridlines on the membrane. However, when forming grid lines, it becomesnecessary to secure regions for forming patterns which had beenoriginally arranged at grid line portions at other positions on themask. Due to this, at least two regions become necessary on the mask.

[0062] Further, since the stencil mask is premised on complementarydivision, as described above, two or more regions are required for onepattern. Namely, in a stencil mask having grid lines, from the points ofview of securing the regions for forming the patterns overlapped withthe grid lines and necessity of complementary division, at least 2×2=4sub-regions become necessary. Therefore, the stencil mask of the presentembodiment is divided into four sub-regions.

[0063] The mask is divided into four sub-regions and given the gridlines 4 in the x-direction or the y-direction not only to solve theproblem of the alignment light being blocked by the grid lines 4 inalignment by the TTR system, but also to evenly arrange the grid lines 4and thereby suppress distortion of the entire mask.

[0064] Also, in each sub-region, the grid lines 4 extend in only onedirection so as to form stripes, so, for example, as shown in FIG. 3,compared to the case where the grid lines are arranged in a mesh and themesh positions are offset from each other in four sub-regions, the gridlines 4 and the other regions (pattern formation regions 5) can bedivided more simply.

[0065] As shown in FIG. 9A, at each sub-region, the parts of the gridlines 4 and the stripe-shaped pattern formation regions 5 arealternately arranged. The total of the number of parts of the grid lines4 and the number of the pattern formation regions 5 (N in thesub-regions A and D, while M in the sub-regions B and C) is an evennumber. The size of each sub-region determined by X and Y of FIG. 9A isa whole multiple of the size of the chip transfer region Ac shown in thesub-region A. Namely, each sub-region includes one or more chip transferregions Ac.

[0066] Each sub-region is provided with mask-side alignment marks 8 atportions corresponding to the four corners of the exposure region. FIG.9B and FIG. 9C are examples of the mask-side alignment marks 8, but themask-side alignment marks 8 are not limited to these shapes. Also, themask-side alignment marks 8 can be either apertures passing through themembrane or recesses formed only in the surface of the membrane.

[0067] The width of the grid lines 4 and the width of the patternformation regions 5 are not necessarily the same, but the totals must bea whole fraction of the length of one side of the chip transfer regionAc and the width of the grid lines 4 must be sufficient for supportingthe membrane. The four corners of the exposure region are provided withalignment optical systems X₁, X₂, Y₁, Y₂-Also, the width of the gridlines 4 extending in the x-direction (grid lines 4 in the sub-regions Band C) and the width of the grid lines 4 extending in the y-direction(grid lines 4 in the sub-regions A and D) are not necessarily the same.In the same manner, the width of the pattern formation regions 5extending in the x-direction (pattern formation regions 5 in thesub-regions B and C) and the width of the pattern formation regions 5extending in the y-direction (pattern formation regions 5 in thesub-regions A and D) are not necessarily the same.

[0068] Unlike the mask shown in FIG. 1 or FIG. 3, in the stencil mask ofthe present embodiment, the membrane at portions surrounded by gridlines is rectangular in shape. This structure easily gives theimpression of being disadvantageous in strength at first glance, butthis is mistaken. The grid line structure of the present embodiment isbased on the theory of material dynamics that “the maximum bendingmoment acting on a rectangular membrane is proportional to the square ofthe short side”.

[0069] The bending moment acting on the membrane fixed at its peripherybecome maximum value M=c(b/a)×a² at a median point of the long side.Here, a is the length of the short side of the rectangle, while b is thelength of the long side of the rectangle. Although the proportionalcoefficient c is a function of the ratio b/a, its dependency on theratio b/a is weak, so it can be regarded as a constant. These aredescribed in the famous textbook on material dynamics, Theory of Platesand Shells (S. P. Timishenko and S. Woinwsky-Krieger), etc.

[0070] Based on this theory, the maximum bending moment when changingthe length b (=a) of a side of a square membrane and the maximum bendingmoment when fixing the length a of one side to 2 mm and changing thelength b of the other side were calculated. The results of thecalculation are shown in FIG. 10. As shown in FIG. 10, in the case of asquare membrane, the load acting on the membrane rapidly increases alongwith an increase in the size.

[0071] On the other hand, in the case of a rectangular membrane, as longas one side is short, even if the long side is made longer, the loadacting on the membrane becomes saturated at a certain value. Asexplained above, the dynamic strength of a rectangular membrane of alength a of a short side is substantially equal to the dynamic strengthof a square membrane of length a of a side. Therefore, according to themask of the present embodiment, the above first condition is satisfied.

[0072] When using the stencil mask of the present embodiment forexposure, regions right below the grid lines cannot be exposed. In FIG.9A, when superposing the stripes parallel to the y-axis in thesub-regions A and D and the stripes parallel to the x-axis in thesub-regions B and C, M×N blocks are obtained. In the example of FIG. 9A,M=N=8. If linking the M×N blocks with a table of M rows×N columns (=8rows×8 columns) to summarize which sub-regions are exposed in each block(namely, in which sub-regions patterns can be formed), the resultbecomes as shown in Table 2. A B B D A B B D A B B D A B B D A C C D A CC D A C C D A C C D A B B D A B B D A B B D A B B D A C C D A C C D A CC D A C C D A B B D A B B D A B B D A B B D A C C D A C C D A C C D A CC D A B B D A B B D A B B D A B B D A C C D A C C D A C C D A C C D

[0073] According to the grid line arrangement of the stencil mask of thepresent embodiment, as shown in Table 2, patterns can be formed in twosub-regions in each block. Therefore, two sub-regions can be linked withany position on a chip. Complementarily divided patterns are formed bybeing allocated to two sub-regions being exposed out of four sub-regionson the same mask. Any device pattern, including donut-like patterns, canbe transferred to a wafer due to multiple exposure superposing foursub-regions. Namely, according to the stencil mask of the presentembodiment, the above second condition is satisfied.

[0074] The direction of the alignment optical system in each sub-regionis parallel to the longitudinal direction of the grid lines 4 in thesub-region. Therefore, as shown in the cross-sectional view of FIG. 11,the optical path of the alignment optical system does not interfere withthe grid lines 4. FIG. 11 is a cross-sectional view showing a patternformation region surrounded by the grid lines 4.

[0075] As shown in FIG. 11, even if the detection angle θ of thealignment light L measured from the mask normal line direction z becomeslarger, according to the arrangement of the optical system shown in FIG.9, the alignment light L (light reflected from the mask-side alignmentmark 8) is not blocked by the grid lines 4. Therefore, it is possible toperform alignment by the TTR system with a high accuracy.

[0076] The method of production of a semiconductor device of the presentembodiment includes a lithography step using the stencil mask of thepresent embodiment. In this lithography step, the wafer stage is movedin increments of X or Y shown in FIG. 9 and exposure repeated afterevery movement. For example, after patterns of the sub-regions A to Dare exposed on the wafer by the first exposure, the wafer stage is movedby exactly the length (X) of the sub-region in the x-direction. In thissituation, if exposing the patterns of the sub-regions A to D on thewafer by second exposure, the patterns of the sub-region B are exposedat the portion where the patterns of the sub-region A were exposed bythe first exposure. Also, the patterns of the sub-region D are exposedat the portion where the patterns of the sub-region C were exposed bythe first exposure.

[0077] After the second exposure, the wafer stage is moved for exampleby exactly the length (Y) of the sub-region in the y-direction (Y). Inthis situation, if exposing the patterns of the sub-regions A to D onthe wafer by third exposure, the patterns of the sub-region B areexposed at the portion where the patterns of the sub-region C wereexposed by the first exposure and the patterns of the sub-region D wereexposed by the second exposure. In this portion, the patterns of thesub-region A are exposed by fourth exposure after moving the waferfurther by exactly a length of −X. Namely, all the patterns of thesub-regions A to D are exposed by first to fourth exposure.

[0078] In actual production of semiconductor devices, a large number ofchips are arranged on a wafer in a matrix. Therefore, instead of movingthe wafer stage in the order of X, Y, −X as described above, it is alsopossible to move the wafer stage in one direction (for example thex-direction) in increments of X from one edge to the other edge, thenmove the wafer stage in the y-direction by exactly Y and move again thewafer stage in the x-direction in increments of −X from one end to theother end.

[0079] The path of movement of the wafer stage can be selected suitablyfor decreasing the time required for movement of the wafer stage. Notethat, if exposing the patterns of the sub-regions A to D each time thewafer is moved, the chips arranged at the outermost positions on thewafer cannot be exposed with the patterns of all of the sub-regionssuperposed, but are exposed with only the patterns of one or twosub-regions. These chips may be discarded.

[0080] As described above, complementarily divided patterns formed inthe four sub-regions A to D are exposed multiply. Also, device patternscan be transferred efficiently to the same number of chips as the numberof the chip transfer regions Ac included in one sub-region. According tothe stencil mask of the present embodiment, the above third condition issatisfied.

[0081]FIG. 12 is a flow chart of the method of production of asemiconductor device of the present embodiment. As shown in FIG. 12, atstep 1 (ST1), the patterns of the first sub-region are exposed by firstexposure. The first sub-region is made one of the four sub-regions onthe mask. Note that the flow chart of FIG. 12 shows the processingperformed on a specific position of a resist coated on a wafer. In thefirst exposure, all the patterns of the first to fourth sub-regions areexposed on the resist comprised of the photosensitive surface on thewafer.

[0082] At step 2 (ST2), the patterns of the second sub-region areexposed by second exposure. The second sub-region is made one of thethree sub-regions other than the first sub-region. Note that, in thesame manner as the first exposure, all the patterns of the first tofourth sub-regions are exposed on the resist on the wafer by the secondexposure too.

[0083] At step 3 (ST3), the patterns of the third sub-region are exposedby third exposure. The third sub-region is made one of the twosub-regions other than the first and second sub-regions. Note that, inthe same manner as the first and second exposure, all the patterns ofthe first to fourth sub-regions are exposed on the resist on the waferby the third exposure too.

[0084] At step 4 (ST4), the patterns of the fourth sub-region areexposed by fourth exposure. The fourth sub-region is made the remainingsub-region other than the first to third sub-regions. Note that, in thesame manner as the first to third exposure, all the patterns of thefirst to fourth sub-regions are exposed on the resist on the wafer bythe fourth exposure, too.

[0085] At step 5 (ST5), the resist is developed. Due to this, thepattern before complementary division is restored and transferred on theresist.

[0086] According to the method of production of a semiconductor deviceof the present embodiment, it is possible to efficiently transferpatterns at each sub-region and expose them with a high throughput whilesuppressing distortion of the mask.

[0087] A stripe-shaped membrane is formed on a SCALPEL mask describedfor example in Japanese Unexamined Patent Publication (Kokai) No.2000-91227. In this mask, the membrane is made more rectangular for thepurpose of decreasing the number of times of making an electron beam orother charged particle exposure beam skip at grid lines when scanning.The direction of the stripes of the membrane is parallel to the scandirection of the charged particle beam.

[0088] In the mask of the present embodiment, the membrane is made morerectangular for a different purpose from the mask described in JapaneseUnexamined Patent Publication (Kokai) No. 2000-91227. For example, inthe mask of the present embodiment, the allowable range of the detectionangle of the alignment light fluctuates corresponding to the height ofthe grid lines. Therefore, the length of the long side of therectangular membrane is suitably determined accordingly.

[0089] As opposed to this, with the SCALPEL mask described in the abovepublication, such a condition was not considered. Further, the maskregion is not divided for forming complementarily divided patterns suchas the sub-regions A to D of the mask of the present embodiment.

[0090] According to the mask of the present embodiment, the grid lines 4do not interfere with the alignment light, so the freedom in design ofthe optical system becomes larger. Therefore, it is also possible to usean optical system having a large numerical aperture (NA) to make thesignal intensity higher. In the case of the conventional mask structureformed with the grid lines 11 in a square mesh as shown in FIG. 1, it isnecessary to change the optical system or make the membrane larger forpreventing the interfere of the alignment light with the grid lines 11.

[0091] However, if enlarging the area of the square membrane, as shownin FIG. 10, the mask strength remarkably declines. Further, change ofthe optical system is also difficult. According to the stencil mask ofthe present embodiment, change of the optical system is not necessaryand the mask strength does not decline.

[0092]FIG. 13 is a top view of a mask when there is a single grid linein each sub-region. In the mask 1 of FIG. 13 as well, the membrane 3 isdivided into four sub-regions by lines (not shown) perpendicularlycrossing at the center of the mask. At an interface portion at which twosub-regions adjoin, a grid line 4 extending along the interface isformed in one sub-region. Due to this, all the grid lines 4 areconnected with each other. The number of grid lines formed in eachsub-region can be either multiple as shown in FIG. 7 or singular asshown in FIG. 13.

[0093] Further, in either case of multiple or singular grid lines ineach sub-region, the size of each sub-region need not be the same. In aregion where the lines are transferred superposed at the same positionof the wafer in all sub-regions, as long as all of the points in theregion are included in a pattern formation region in at least twosub-regions, the sizes and shapes of the sub-regions can also bedifferent. However, from the viewpoint of decreasing the distortion ofthe entire mask, as shown in FIG. 1 or FIG. 13, it is preferable to makethe sub-regions the same in size and form grid lines point symmetricallyin sub-regions located on the diagonal.

[0094] When forming complementarily divided patterns on a plurality ofcomplementary masks and transferring the patterns complementarily bymultiple exposure using the complementary masks, it is necessary toexchange the complementary masks mounted in the exposure system. Here,the “complementary masks” mean a plurality of masks formed withdifferent patterns (complementarily divided patterns) comprised of partsof patterns obtained by dividing the pattern of a certain region. Byexposing specific regions of the complementary masks superposed at thesame place of the exposed object (usually a wafer), the pattern beforedivision is restored and transferred to the exposed object.

[0095] As opposed to this, according to the stencil mask of the presentembodiment, complementarily divided patterns are formed at differentsub-regions of the same mask. Therefore, when exposing thecomplementarily divided patterns, it is not necessary to exchange themask mounted in the exposure system and it is possible to performmultiple exposure on chips just by moving the wafer stage. Therefore,compared with the case of forming the complementarily divided patternson different masks, the throughput of exposure can be greatly improved.

[0096] Further, the number of sub-regions formed in the stencil mask ofthe present embodiment is not limited to four. For example, it ispossible to divide the membrane into 16 sub-regions as shown in FIG. 14,divide the membrane into nine sub-regions as shown in FIG. 15, or dividethe membrane into six sub-regions as shown in FIG. 16.

[0097] When dividing the membrane into other than four sub-regions, thedirections in which the grid lines extend are made perpendicular to eachother between adjacent sub-regions. When making the number ofsub-regions more than four, it is possible to form in the increasednumber of sub-regions complementarily divided patterns similar to thefour sub-regions A to D, form other complementarily divided patterns, orform pattern for exposure other than complementarily divided patterns.

[0098] According to the mask and the method of production of asemiconductor device of the present invention, when performing alignmentby the TTR system, the alignment light is not blocked by the grid lines.Therefore, even in LEEPL in which the wafer and mask are brought closein proximity, it becomes possible to perform alignment with a highaccuracy. Also, according to the method of production of a mask of theembodiment of the present invention, it becomes possible to produce amask suitable for both alignment by the TTR system and transfer ofcomplementarily divided patterns.

[0099]FIG. 17 is a schematic view of an exposure apparatus used forLEEPL and shows a projection optical system of an electron beam. Thestencil mask of the present embodiment can be suitably used for electronbeam exposure by the exposure apparatus as shown in FIG. 17.

[0100] The exposure apparatus 111 of FIG. 17 has an electron gun 113 forgenerating an electron beam 112 and also an aperture 114, condenser lens115, pair of main deflectors 116 and 117, and pair of fine adjustmentdeflectors 118 and 119.

[0101] The aperture 114 limits the electron beam 112. The condenser lens115 converts the electron beam 112 into a parallel beam. The sectionalshape of the electron beam 112 condensed by the condenser lens 115 isnormally a circle, but may be another sectional shape as well. The maindeflectors 116 and 117 and the fine adjustment deflectors 118 and 119are deflector coils. The main deflectors 116 and 117 deflect theelectron beam 112 so that the electron beam 112 strikes the surface ofthe stencil mask 120 basically perpendicularly.

[0102] The fine adjustment deflectors 118 and 119 deflect the electronbeam 112 so that the electron beam 112 strikes the surface of thestencil mask 120 perpendicularly or inclined slightly from theperpendicular direction. Although the angle of incidence of the electronbeam 112 is optimized according to the pattern position on the stencilmask 120 etc., the angle of incidence of the electron beam 112 is about10 mrad even at the maximum. The electron beam 112 strikes the stencilmask 120 substantially perpendicularly.

[0103] The electron beams 112 a to 112 c shown in FIG. 17 show the statewhere the electron beam 112 scanning the stencil mask strikes positionson the stencil mask substantially perpendicularly and do not show thestate where the electron beams 112 a to 112 c simultaneously strike thestencil mask 120. The scan by the electron beam 112 may be either of araster scan or vector scan.

[0104] In FIG. 17, the resist 123 on the wafer 122 is exposed by theelectron beam passing through the hole 121 parts of the stencil mask120. For LEEPL, equal magnification masks are used. The stencil mask 120and wafer 122 are arranged in proximity.

[0105] At that time of electron beam exposure by the above-mentionedexposure system 111, the stencil mask of the present embodiment is usedas the stencil mask 120. In the stencil mask according to the presentembodiment, the membrane is reinforced by the grid lines so flexing ofthe membrane is prevented and positional deviation of transfer patternsin the electron beam exposure is reduced. Also, complementarily dividedpatterns can be exposed with superposition without changing the stencilmask 120 due to moving the wafer.

[0106] The stencil mask having an arrangement of grid lines shown in theabove embodiment can also be applied to other electron beam exposuresystems other than LEEPL, for example an electron beam exposure systemshown in FIG. 18. According to the projection optical system shown inFIG. 18, the patterns of the mask 201 are transferred reduced by apredetermined magnification to a wafer or other sample 202 etc., usingan electron beam. The path of the electron beam is controlled by acondenser lens 203, first projection lens 204, second projection lens205, crossover aperture 206, sample lens 207, and a plurality ofdeflectors 208 a to 208 i.

[0107] In the projection optical system shown in FIG. 18, a deflectionmagnetic field is generated from the plurality of deflectors 208 so thatthe electron beam passing through the mask 201 passes through thecrossover aperture 206 and perpendicularly strikes the sample 202. Themask of the present embodiment can also be used for other exposuresystems using an ion beam or other charged particle beam in addition tothe electron beam exposure system having the above projection opticalsystem. Further, the mask of the present embodiment can also be used forexposure systems using X-rays, radiation, or light rays.

[0108] The embodiments of the mask, the method of production of a mask,and the method of production of a semiconductor device of the presentinvention are not limited to the above explanation. For example, it issufficient that the grid lines of the mask be formed in stripeshapes—the material and configuration of the mask can be suitablymodified. Specifically, the membrane can be provided with anelectroconductive layer for preventing charge up or the mask can befabricated by another method than the above. The stencil mask of thepresent embodiment can also be used for another process of production ofa semiconductor device than lithography, for example ion implantation.In addition, various modifications can be made within a scope notexceeding the gist of the present invention.

[0109] According to the mask of the present invention, alignment by theTTR system and transfer of complementarily divided patterns are possibleand a sufficient membrane strength can be obtained.

[0110] According to the method of production of a mask of the presentinvention, alignment by the TTR system and transfer of complementarilydivided patterns are possible and a mask having a sufficient membranestrength can be produced.

[0111] According to a method of production of a semiconductor device ofthe present invention, the accuracy of alignment in the lithography stepis improved and it becomes possible to transfer fine patterns with ahigh accuracy.

1. A mask comprising: a support frame; a thin film made formed thinnerthan said support frame and surrounded by said support frame; a firstsub-region of a plurality of sub-regions obtained by dividing said thinfilm by a plurality of lines including a first line passing through areference point consisting of one point on said thin film and extendingin a first direction and a second line orthogonal to the first line atthe reference point and extending in a second direction; a secondsub-region adjacent to said first sub-region in the first direction; athird sub-region adjacent to said first sub-region in the seconddirection; a fourth sub-region adjacent to said second sub-region in thesecond direction and adjacent to said third sub-region in the firstdirection; a first group of grid lines comprised of at least one gridline extending on said first sub-region in the second direction andhaving one end connected to one of a third group of grid lines toreinforce said thin film, said first group of grid lines including agrid line contacting the second line; a second group of grid linescomprised of at least one grid line extending on said second sub-regionin the first direction and having one end connected to one of said firstgroup of grid lines to reinforce said thin film, said second group ofgrid lines including a grid line contacting the first line; said thirdgroup of grid lines comprised of at least one grid line extending onsaid third sub-region in the first direction and having one endconnected to one of a fourth group of grid lines to reinforce said thinfilm, said third group of grid lines including a grid line contactingthe first line; said fourth group of grid lines comprised of at leastone grid line extending on said fourth sub-region in the seconddirection and having one end connected to one of said second group ofgrid lines to reinforce said thin film, said fourth group of grid linesincluding a grid line contacting the second line; a first apertureformed at a part of a portion other than the grid lines in the firstsub-region; and a second aperture formed at a part of a portion otherthan the grid lines in at least one sub-region of the second to fourthsub-regions.
 2. A mask as set forth in claim 1, wherein the firstaperture and the second aperture form patterns complementarily.
 3. Amask as set forth in claim 1, wherein the grid lines are formed at equalintervals in each of the first to fourth sub-regions.
 4. A mask as setforth in claim 3, wherein a space between the grid lines of the thirdgroup is equal to the space between the grid lines of the second group.5. A mask as set forth in claim 4, wherein a space between the gridlines of the fourth group is same as a space between the grid lines ofthe first group.
 6. A mask as set forth in claim 1, wherein the first tofourth sub-regions are squares or rectangles the same as each other inshape and size.
 7. A mask as set forth in claim 1, wherein the gridlines of at least one of group among the first to fourth groups areformed to having other ends connected to the support frame.
 8. A mask asset forth in claim 1, wherein the first and second apertures are holesthrough which a charged particle beam passes.
 9. A mask as set forth inclaim 1, wherein the first to fourth sub-regions are divided into aplurality of chip transfer regions the same in shape and size by atleast one first division line parallel to the first line and at leastone second division line parallel to the second line.
 10. A mask as setforth in claim 1, comprising an alignment mark formed at a part of aportion other than the grid lines in the first to fourth sub-regions.11. A mask as set forth in claim 10, wherein the alignment mark isformed at a furthest part from the reference point in each sub-region.12. A method of production of a mask comprising the steps of: forming asupport frame around a thin film, forming grid lines reinforcing saidthin film at a part on one surface of said thin film, and formingapertures in the thin film at portions other than the grid lines,wherein said step of forming the grid lines comprising the step offorming a first group of grid lines in a first sub-region of said thinfilm, forming a second group of grid lines in a second sub-region ofsaid thin film, forming a third group of grid lines in a thirdsub-region of said thin film, and forming a fourth group of grid linesin a fourth sub-region of said thin film; said first sub-region is oneof a plurality of sub-regions obtained by dividing said thin film by aplurality of lines including a first line passing through a referencepoint consisting of one point on said thin film and extending in a firstdirection and a second line perpendicular to the first line at thereference point and extending in a second direction; said secondsub-region is a sub-region adjacent to said first sub-region in thefirst direction, said third sub-region is a sub-region adjacent to saidfirst sub-region in the second direction, said fourth sub-region is asub-region adjacent to said second sub-region in the second directionand adjacent to said third sub-region in the first direction, said firstgroup of grid lines is comprised of at least one grid line extending onthe first sub-region in the second direction and having one endconnected to one of a third group of grid lines to reinforce the thinfilm and including a grid line contacting the second line, said secondgroup of grid lines is comprised of at least one grid line extending onthe second sub-region in the first direction and having one endconnected to one of the first group of grid lines to reinforce the thinfilm and includes a grid line contacting the first line, said thirdgroup of grid lines is comprised of at least one grid line extending onthe third sub-region in the first direction and having one end connectedto one of a fourth group of grid lines to reinforce the thin film andincludes a grid line contacting the first line, said fourth group ofgrid lines is comprised of at least one grid line extending on thefourth sub-region in the second direction and having one end connectedto one of the second group of grid lines to reinforce the thin film andincludes a grid line contacting the second line, and the step of formingthe apertures comprises forming a first aperture at a part of a portionother than the grid lines in the first sub-region and forming a secondaperture at a part of a portion other than the grid lines in at leastone sub-region of the second to fourth sub-regions.
 13. A method ofproduction of a semiconductor device comprising an exposure step ofirradiating a charged particle beam, radiation, or a light ray on aphotosensitive surface via a mask, comprising: a first exposure step ofirradiating a charged particle beam, radiation, or a light ray on aphotosensitive surface via a mask comprising: a support frame, a thinfilm made formed thinner than said support frame and surrounded by saidsupport frame, a first sub-region of a plurality of sub-regions obtainedby dividing said thin film by a plurality of lines including a firstline passing through a reference point consisting of one point on saidthin film and extending in a first direction and a second lineorthogonal to the first line at the reference point and extending in asecond direction, a second sub-region adjacent to said first sub-regionin the first direction, a third sub-region adjacent to said firstsub-region in the second direction, a fourth sub-region adjacent to saidsecond sub-region in the second direction and adjacent to said thirdsub-region in the first direction, a first group of grid lines comprisedof at least one grid line extending on said first sub-region in a seconddirection and having one end connected to one of a third group of gridlines to reinforce said thin film, said first group of grid linesincluding a grid line contacting the second line, a second group of gridlines comprised of at least one grid line extending on said secondsub-region in a first direction and having one end connected to one ofsaid first group of grid lines to reinforce said thin film, said secondgroup of grid lines including a grid line contacting the first line,said third group of grid lines comprised of at least one grid lineextending on said third sub-region in the first direction and having oneend connected to one of a fourth group of grid lines to reinforce saidthin film, said third group of grid lines including a grid linecontacting the first line, said fourth group of grid lines comprised ofat least one grid line extending on said fourth sub-region in a seconddirection and having one end connected to one of said second group ofgrid lines to reinforce said thin film, said fourth group of grid linesincluding a grid line contacting the second line, a first apertureformed at a part of a portion other than the grid lines in the firstsub-region, and a second aperture formed at a part of a portion otherthan the grid lines in at least one sub-region of the second to fourthsub-regions, said first exposure step conducting the first exposuresuperposing the first sub-region at a predetermined position of thephotosensitive surface to transfer the first aperture in thepredetermined position, and a second exposure step of performing secondexposure superposing one of the sub-regions including the secondaperture to a predetermined position to transfer the second aperture inthe predetermined position.
 14. A method of production of asemiconductor device as set forth in claim 13, further comprising: athird exposure step of performing third exposure superposing asub-region, not superposed at said predetermined position in said firstand second exposures and having a third aperture, at said predeterminedposition to transfer the third aperture in said predetermined positionand a fourth exposure step of performing fourth exposure superposing asub-region not superposed at said predetermined position in said firstto third exposures and having a fourth aperture, at said predeterminedposition to transfer the fourth aperture in said predetermined position.15. A method of production of a semiconductor device as set forth inclaim 13, wherein: said mask comprises a mask-side alignment mark at apart of a portion other than the grid lines in the first to fourthsub-regions and said method further comprising: before said firstexposure step, forming in advance a wafer-side alignment mark detectablevia the mask on said photosensitive surface or beneath saidphotosensitive surface and comprising, before each exposure step, atleast one of the steps of: irradiating light in the first direction to asub-region including said grid lines extending in the first direction soas to detect positions of light reflected from the mask-side alignmentmark and light reflected from the photosensitive surface-side alignmentmark to align the mask and the photosensitive surface and irradiatinglight in the second direction to a sub-region including said grid linesextending in the second direction so as to detect positions of lightreflected from the mask-side alignment mark and light reflected from thephotosensitive surface-side alignment mark to align the mask and thephotosensitive surface.
 16. A method of production of a semiconductordevice as set forth in claim 14, wherein: said mask comprises amask-side alignment mark at a part of a portion other than the gridlines in the first to fourth sub-regions and said method furthercomprising: before said first exposure step, forming in advance awafer-side alignment mark detectable via the mask on said photosensitivesurface or beneath said photosensitive surface and comprising, beforeeach exposure step, at least one of the steps of: irradiating light inthe first direction to a sub-region including said grid lines extendingin the first direction so as to detect positions of light reflected fromthe mask-side alignment mark and light reflected from the photosensitivesurface-side alignment mark to align the mask and the photosensitivesurface and irradiating light in the second direction to a sub-regionincluding said grid lines extending in the second direction so as todetect positions of light reflected from the mask-side alignment markand light reflected from the photosensitive surface-side alignment markto align the mask and the photosensitive surface.
 17. A method ofproduction of a semiconductor device as set forth in claim 13, whereinthe alignment mark is formed at a furthest part from the reference pointin each sub-region.
 18. A method of production of a semiconductor deviceas set forth in claim 13, wherein the alignment is conductedconcurrently with the exposure.